1. Field of the Invention
The present invention relates in general to a phase locked loop (PLL) circuit, and more particularly to a PLL circuit in which a locked operation is performed at a high speed.
2. Description of the Prior Art
Generally, a PLL circuit is a closed circuit which generates a signal synchronized in phase and frequency with an input signal, and used in various forms in many types of equipment such as a communication radar, a computer, a frequency control instrumentation device, etc.
FIG. 1 is a block diagram of a conventional PLL circuit. As shown in this drawing, the conventional PLL circuit comprises an R counter 101 for dividing an input reference frequency F.sub.Ref by R, an N counter 102 for dividing an output of the PLL circuit fed back thereto by N. A phase detector 103 compares the phases of outputs F.sub.R and F.sub.N from the R and N counters 101 and 102, respectively, and outputs the resultant difference. A low pass filter (LPF) 104 is provided to low pass filter the output of the phase detector 103. A voltage controlled oscillator (VCO) 105 is provided for generating a frequency signal proportioned to a voltage value from the LPF 104.
Such a conventional PLL circuit remains in its locked state when the outputs F.sub.R and F.sub.N from the R and N counters 101 and 102, respectively, are synchronized with each other in phase and frequency. The R and N counters 101 and 102 may have the dividing factors R and N fixed or set by externally loaded values as needed. Time is required for a transition from an initial unlocked state to a locked state. If the outputs F.sub.R and F.sub.N from the R and N counters 101 and 102 have the same frequency but are out of phase during the transition from the initial unlocked state to the locked state, the VCO 105 changes the frequency and readjusts it when the signals are in phase, so that the PLL circuit becomes locked.
The above-mentioned conventional PLL circuit has a disadvantage in that the phase detector compares the signals F.sub.R and F.sub.N obtained by dividing the input frequencies with each other, resulting in an increase in the time required for the transition from the unlocked state to the locked state. For this reason, most types of equipment employing the PLL circuit have a response characteristic which is retarded due to the long locking time required.